An integrated circuit (IC) typically includes an IC chip, which is housed in a plastic, ceramic, or metal "package". The IC chip includes an integrated circuit formed on a thin wafer of silicon. The package supports and protects the IC chip and provides electrical connections between the integrated circuit and an external circuit or system.
There are several package types, including ball grid arrays (BGA's), pin grid arrays (PGA's), plastic leaded chip carriers (PLCC's), and plastic quad flat packs. Each of the package types is typically available in numerous sizes. The package type selected by an IC manufacturer for a particular IC chip is typically determined by the size/complexity of the IC chip (i.e. the number of input/output terminals), and also in accordance with a customer's requirements.
FIGS. 1a and 1b show bottom and side sectional views of a typical BGA IC 100, which includes an IC chip 110 mounted on an upper surface 122 of a package substrate 120. Electrical connections between bonding pads of IC chip 110 and conductive lines (not shown) formed on substrate 120 are provided by bond wires 150. A plurality (twenty-five shown) of solder balls (sometimes referred to as solder bumps or solder dots) 140 are electrically connected to the conductive lines and extend from a lower surface 124 of substrate 120. Electrical signals travel between each solder ball 140 and one bonding pad of IC chip 110 along an associated conductive line and bond wire 150. A cover 130, such as a cap or "glob top", is placed or formed over IC chip 110 and bond wires 150 for protection.
IC manufacturers use an IC testing system to test their IC's before shipping them to customers. An IC testing system typically includes a device tester, a device handler, and an interface structure. The device tester is an expensive piece of computing equipment, which transmits test signals via tester probes to an interface structure. The interface structure transmits signals between the leads of an IC under test and the device tester. The device handler is an expensive precise robot for automatically moving IC's from a storage area to the interface structure and back to the storage area.
FIGS. 2a and 2b show side and top views of a conventional interface structure 200, which is used to test BGA IC's. Interface structure 200 includes a disk-shaped printed circuit board (PCB) 210 and a contactor 300. PCB 210 includes groups of outer vias 220, which are spaced around the perimeter of PCB 210. Outer vias 220 receive male tester probes extending from the device tester (not shown). Outer vias 220 are connected by metal traces (conductive lines) 230 to inner sockets 240 located in a central test area. Contactor 300 is mounted over the central test area such that pin terminals (discussed in further detail below) which extend from a lower surface of the contactor 300 are received in the sockets 240. After a BGA IC is mounted on contactor 300 by the device handler, the device tester transmits test signals through the male tester probes (not shown) to the outer vias 220, along traces 230 to the sockets, and finally through contactor 300 to the BGA IC under test. Similarly, return signals from the BGA IC are transmitted to the test device through contactor 300, socket 240, traces 230, and outer vias 220.
FIGS. 3a and 3b show top and side sectional views of a contactor 300. Contactor 300 includes a housing 310 and a nesting member 320 movably mounted on housing 310 via support springs 330. Housing 310 includes lower wall 312, side walls 314 extending upward around the periphery of lower wall 312, and spring mounts 316 for receiving one end of support springs 330. A peripheral edge of nesting member 320 is surrounded by outer side walls 314 of housing 310, thereby limiting horizontal movement of nesting member 320. However, a small gap G1 is provided between nesting member 320 and side walls 314 to allow vertical movement. Nesting member 320 includes a plate portion 322 positioned over the lower wall 312 of housing 310, and raised alignment walls 323 located at two corners of plate portion 322 which define a receiving area for BGA IC 100 (indicated in dashed lines). Plate portion 322 includes an indented area 324 having an upper surface 325, a lower surface 326, and a plurality of through-holes 328. Contactor 300 also includes a plurality of C-spring contacts 340 each having a C-shaped spring portion 342. Each spring contact 340 includes a contact portion 344 which extends through one of the through-holes 328 of nesting member 320, and a pin terminal 346 which extends through lower wall 312 of housing 310. When contactor 300 is mounted onto PCB 210, pin terminals 346 are received in sockets 240 formed in PCB 210.
While C-spring contacts 340 have been shown in FIG. 3b, several alternative methodologies exist for providing electrical contact with BGA IC 100 (indicated by dashed lines). A few of the more common methodologies include an S-spring contact 347, as shown in FIG. 3c, a fuzz button contact 348, as shown in FIG. 3d, and a pogo pin contact, as shown in FIG. 3e. However, all conventional methodologies share similar performance characteristics and issues.
Operation of conventional interface structure 200 is described with reference to FIGS. 4a and 4b. As shown in FIG. 4a, a device handler (not shown) places BGA IC 100 (shown in silhouette) onto nesting member 320 with solder balls 140 extending into indented area 324. BGA IC 100 is aligned on nesting member 320 by contact between the peripheral edge of BGA IC 100 and raised alignment walls 323 of nesting member 320. This alignment is intended to position solder balls 140 over the contact portions 344 of spring contacts 340. Subsequently, as shown in FIG. 4b, the device handler presses BGA IC 100 downward (in the direction indicated by arrow Z) against the force exerted by support springs 330. As nesting member 320 is displaced downward, solder balls 140 move toward and abut contact portions 344. Further downward force is absorbed by the spring portion of spring contacts 340. When BGA IC 100 is properly aligned, electrical signals are then transmitted between PCB 210 and BGA IC 100 through contact between solder balls 140 and contact portions 344 of spring contacts 340. The device handler then removes BGA IC 100, and nesting member 320 is biased into its original position by support springs 330.
Several problems are associated with conventional interface structure 200, and in particular, to conventional contactor 300.
First, contactor 300 is expensive (approximately $500 or more) and also very fragile. Pin terminals 346 of spring contacts 340 are often bent or damaged when contactor 300 is mounted to PCB 210. Straightening or replacing bent pin terminals 346 is extremely time-consuming, and therefore IC testing system operators often simply discard damaged contactors. Further, due to their simple construction, spring contacts 340 typically weaken and fail after a relatively low number of test procedures. As a result, device testing using conventional interface structures is expensive and often time-consuming.
A second problem associated with conventional interface structure 200 is described with reference to FIG. 4c. Nesting member 320 can become misaligned due to temperature variations. Interface structures are typically mounted on device testers at room temperature. Subsequent testing procedures are often performed at much higher temperatures. This temperature difference causes deformation of spring contacts 340, which shift nesting member 320 horizontally relative to housing 310 (indicated in FIG. 4c by a gap G2, which is larger than gap G1 shown in FIG. 3b). Because the device handler is adjusted to mount BGA IC 100 in the original (room temperature) position of nesting member 320, this shift results in a relative misalignment between BGA IC 100 and nesting member 320. Alternatively, due to repeated lateral motion when BGA IC's 100 are inserted and removed from nesting member 320, nesting member 320 may become permanently biased to one side. Also, manufacturing inaccuracies can cause nesting member 320 to be misaligned from the beginning. In some cases, as shown in FIG. 4c, BGA IC 100 is mounted such that one corner is located on top of alignment wall 323. When this occurs, subsequent downward pressure by the device handler often destroys BGA IC 100. Unless this problem is quickly recognized and corrected, significant product loss can occur. One possible solution to this problem is to widen alignment wall 323 and provide a long, tapered surface such that BGA IC's slide easily into position on nesting member 320. However, because the overall width of contactor 300 is typically restricted, and because a portion of this width is occupied by side walls 314 of housing 310, the width of nesting member 320 (and, therefore, alignment wall 323) is limited.
A third problem associated with conventional interface structure 200 is described with reference to FIG. 4d. In particular, alignment within nesting member 320 is based on the outer peripheral shape of BGA IC 100. If the position of solder balls 140 relative to the outer edge of substrate 120 (shown in FIG. 1a) is shifted during package manufacturing, the resulting misalignment can result in total misalignment between contact portions 344 and solder balls 140, as shown in FIG. 4d.
Further, partial misalignment between solder balls 140 and contact portions 344 can cause BGA IC 100 to become wedged (stuck) to contact members 342 as shown in FIG. 5a. As BGA IC 100 is pressed downward, the partial misalignment causes contact portions 344 to slide along the outer sloped edge of solder balls 140, thereby causing deflection of contact portions 344 against plate portion 322 surrounding through-holes 328. This wedging action can resist subsequent upward movement of BGA IC 100, thereby causing BGA IC 100 to become disengaged from the device handler, and causing a costly shut-down of the testing process.
A final problem associated with conventional interface structure 200 is described with reference to FIGS. 5b and 5c. In particular, because of the various alignment problems associated with conventional interface structure 200 (discussed above), it is required to utilize a relatively wide contact portion 344(1) shown in FIG. 5b, or a cup-shaped contact portion 344(2) shown in FIG. 5c to ensure contact with solder balls 140. However, the flat upper surface 345 of contact portion 344(1) serves as a ledge upon which tin-lead contamination 346 from solder balls 140 deposits over a period of time. Similarly, the cup-shaped contact portion 344(2) collects tin-lead contamination 346. Tin-lead contamination 346 imposes a resistance between contact portions 344(1) and 344(2) and solder ball 140, thereby causing incorrect test results and the erroneous discarding of good parts.
Currently, the trend in industry is towards smaller IC chips having a greater number of bonding pads. At the same time, IC size requirements are also shrinking. As a result, miniature IC's are becoming increasingly more difficult to produce using traditional IC packaging methods. Not only do the traditional methods have difficulty accommodating the dense bonding pad arrangements of the smaller IC chips, but the "traditional" package substrate is significantly larger than the IC chip, further inhibiting the trend towards miniaturization. These decreasing IC chip packaging size requirements have led to the development of "chip scale" packaging methodologies such as micro ball grid array (.mu.BGA) packaging and chip scale packaging (CSP). These packaging methodologies are characterized by the fact that the IC chip package is essentially the same size as the IC chip, or that electrical connections such as solder balls or solder columns are attached directly to the bonding pads of the IC chip. Whereas a conventional BGA IC might provide 1.27 mm from solder ball center to solder ball center, a "chip scale" package can have less than 0.5 mm between adjacent solder balls.
FIGS. 12a and 12b show an IC 1200 that is consistent with "chip scale" packaging methodologies. IC 1200 includes an IC chip 1210 that has a plurality of bonding pads (not shown) formed thereon, and a plurality of solder balls 1220 that are directly attached to the bonding pads. This direct connection causes the density of electrical connections provided by IC 1200 to be the same as that of the bonding pads on IC chip 1210. As a result, the traditional methods of testing BGA IC's (discussed above) cannot be used to test "chip scale" IC's because it is not physically possible to pack the C-spring contacts (shown in FIG. 3b), the S-spring contacts (shown in FIG. 3c), the fuzz button contacts (shown in FIG. 3d), or the pogo pins (shown in FIG. 3e) closely enough to reliably contact the high-density solder balls.
IC manufacturing, regardless of chip size, involves producing multiple dies on a single wafer and then singulating them into individual IC chips. IC chips are typically tested while still in wafer form, using a technique known as "wafer probing". Historically, wafer probing has been performed using a wafer testing system 600, as shown in FIG. 6. A processed wafer 610 made up of a plurality of dies 612 is mounted on a wafer support structure 620. A precision placement robot 630 positions a lateral probe assembly 640 over one of the plurality of dies 612 and then lowers probe assembly 640 until electrical contact is made with the bonding pads on die 612. Probe assembly 640 then transmits test signals between die 612 and a test controller (not shown). Placement robot 630 then raises probe assembly 640 from die 612 and positions itself over another of the plurality of dies 612 to be tested.
Typically, referring to FIGS. 7a and 7b, a probe assembly 640 includes a lateral probe assembly 700. Lateral probe assembly 700 includes a PCB 710 and a grouping of probe leads 720 in a central opening 712 of PCB 710. Each probe lead 720 extends into central opening 712, angling downward and tapering to a small probe tip 722. Probe tips 722 are arranged in a pattern matching the layout of bonding pads on the dies to be tested. When lateral probe assembly 700 is lowered onto a die, probe tips 722 contact the bonding pads on the die to provide an electrical connection. Further downward force is absorbed by the flexibility of probe leads 720. Probe leads 720 are connected by metal traces (not shown) to outer vias 730. The test controller transmits and receives signals through male tester probes (not shown) mounted into outer vias 730.
As bonding pad densities increase, probe leads 720 must undergo a corresponding size reduction, increasing the risk of lead damage during handling and test. In addition, due to the planar construction of lateral probe assembly 700, only dies having peripherally-located bonding pads can be tested. Therefore, the grid patterns of bonding pads in high-density IC wafers are problematic for conventional wafer test systems.
A recent development in wafer testing enables the testing of high-density IC wafers. FIGS. 8a and 8b show a vertical probe assembly 800 that includes a vertical probe card 820 mounted on the bottom surface of a PCB 810. A group of probe tips 822 protrude substantially normally from a lower surface 824 of vertical probe card 820. Each probe tip 822 is part of a formed wire probe (not shown) mounted within vertical probe card 820. The formed wire probe includes a spring section (not shown) to bias its probe tip 822 away from lower surface 824. The use of fine-diameter wire for the formed wire probes enables a high-density array of probe tips 822 to be provided by vertical probe card 820. As a result, vertical probe assembly 800 can replace lateral probe assembly 700 in wafer testing system 600 in order to test wafer scale dies. When vertical probe assembly 800 is lowered onto a die, probe tips 822 contact the bonding pads on the die to provide an electrical connection. Further downward force is absorbed by the spring sections of the formed wire probes. Metal traces (not shown) on PCB 810 connect the formed wire probes to outer vias 830. The test controller (not shown) transmits and receives signals through male tester probes (not shown) mounted into outer vias 830.
However, although the vertical probe card allows the dies of a wafer to be tested, no apparatus or method currently exists for testing "chip scale" IC's (i.e., after wafer dicing). Accordingly, it is desirable to provide an apparatus and method for reliably testing .mu.BGA and CSP IC's.